1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and, more particularly. a semiconductor device manufacturing method including the step of forming a shallow trench isolation (STI).
2. Description of the Prior Art
In recent years, with the progress of miniaturization in the semiconductor device, it has become difficult to isolate devices with good precision by using the device isolation method which employs the LOCOS (Local Oxidation of Silicon) method employed in the prior art.
For this reason, the method using the shallow trench has engaged public attention as the new device isolation method in place of the LOCOS method, and has already been utilized.
FIGS. 1A to 1G are sectional views showing steps of forming shallow trenches in the prior art.
First, as shown in FIG. 1A, an oxide film 5 and a nitride film 6 are formed on a surface of a silicon substrate 1 in this sequence.
Then, as shown in FIG. 1B, the oxide film 5 and the nitride film 6 are removed from a region serving as a device isolation region by the photolithography method.
Then, as shown in FIG. 1C, the silicon substrate 1 is etched by using the oxide film 5 and the nitride film 6 as a mask to form shallowly a first trench 3a to a fourth trench 3d which have a different width respectively. At this time, because the silicon substrate 1 is partitioned by the trenches 3a to 3d, regions partitioned by the first trench 3a and the fourth trench 3d with a wide area respectively are first device regions 2a each of which has a wide area, a region partitioned by the second trench 3b with a middle width is a second device region 2b which has a middle area, and a region partitioned by the third trench 3c with a narrow width is a third device region 2c which has a convex narrow area.
Then, as shown in FIG. 1D, a silicon oxide film 7 whose thickness is thicker than depths of the first trench 3a to the fourth trench 3d is formed on the silicon substrate 1 to bury the first trench 3a to the fourth trench 3d. In this case, if the silicon oxide film 7 is formed under the condition that such silicon oxide film 7 can be buried densely in the third trench 3c with the narrow width, normally a thickness of the silicon oxide film 7 becomes thickest on the first device region 2a which has the large width but becomes thinnest on the third device region 2c which has the small width. In addition, a thickness t3 of the silicon oxide film 7 formed in the region, in which the third trenches 3c having the small width are formed collectively, is larger than thicknesses t1, t2 of the silicon oxide film 7 in the first trench 3a and the second trench 3b both have the large width.
Then, as shown in FIG. 1E, a photoresist film 8 is formed on an overall surface, Windows 9a, 9b are then formed by exposing and developing the photoresist film 8. These windows 9a, 9b are positioned over the first device region 2a which has the large width and the second device region 2b which has the middle width respectively.
Then, the silicon oxide film 7 is etched via the windows 9a, 9b. In this case, an etching depth of the silicon oxide film 7 may be set shallow not to expose the nitride film 6.
Then, as shown in FIG. 1F, the photoresist film 8 is removed. Then, as shown in FIG. 1G, a surface of the silicon oxide film 7 is polished. In this event, polishing of the silicon oxide film 7 formed on the first device region 2a and the second device region 2b can be easily performed, and then such polishing is substantially stopped by the nitride film 6. Accordingly, the silicon oxide film 7 can be buried in the first trench 3a to the fourth trench 3d, but the silicon oxide film 7 can be removed from the first device region 2a to the third device region 2c.
The first trench 3a to the fourth trench 3d in which the silicon oxide film 7 is buried can act as a shallow trench to isolate the first device region 2a to the third device region 2c respectively.
In the above-mentioned steps, the reason for that the width of the silicon oxide film 7 formed on the first device region 2a and the second device region 2b is made small is to planarize a polished surface of the silicon oxide film 7 by accelerating the polishing of the silicon oxide film 7 on the region which has the thicker silicon oxide film 7. In other words, if the silicon oxide film 7 is left thick on the first device region 2a which has the largest width and the second device region 2b which has the middle width, it is difficult to achieve uniform polishing since a polishing resistance in such regions 2a and 2b is increased.
Meanwhile, according to the above shallow trench forming method, since a plurality of different steps such as the photolithography step, the etching step, and the polishing step are needed, the number of steps of manufacturing the semiconductor device is increased.
Also, if variation of the silicon oxide film 7 in film thickness is generated, the silicon oxide film 7 is left on the first device region 2a and the second device region 2b after the etching, or else the film thickness of the silicon oxide film 7 which is left on the first device region 2a and the second device region 2b is varied. Hence, according to the above method, variation of the film thickness of the silicon oxide film 7 cannot be overcome.
Furthermore, if the silicon oxide film 7 is assumed to be uniform, variation in etching of a surface of the silicon oxide film 7 shown in FIG. 2 is generated when STI is formed on, e.g., twenty five sheets of the semiconductor wafers, so that the thickness of the silicon oxide film 7 being left on the semiconductor wafer is ready to be uneven.
In the situation that the silicon oxide film 7 has its uneven thickness on the first device region 2a to the third device region 2c respectively, if polishing of the silicon oxide film 7 is carried out until it is removed completely from the first device region 2a to the third device region 2c, an upper surface of the silicon oxide film 7 is curved in the first trench 3a to the fourth trench 3d like a dishing since such polishing is also proceeded in the first trench 3a to the fourth trench 3d.